@07@February 10, 1994



Technical notes for ROM1

This is a brief, informal discussion of the basic features and
operation of the ROM1 EPROM Emulator.


SOFTWARE:

ROM1.exe is the full-screen, interactive editor. It has:

        - Support for 1, 2, or 4 emulators
        - Increased upload and download performance to 250 Kbits/sec
        - Increased file load performance by 300%
        - Added a "Go to Offset" command
        - Changed the editor to handle files up to 2 MBytes in length
        - Added a ROM1.CFG file to "remember" configuration options
          This is a binary file maintained by the program.  It is
          automaticaly created and maintained.
        - Added a "disable" option for the symaphore byte
        - Modified configuration screen to support the new options

ROM1 uses a temporary file called ROM1.wrk. This file will be the
same size as any file loaded into the editor.  All file modification
are performed on this file instead of the original.  If the user chooses
to save the editor, the original file is renamed *.BAK and the temporary
file is renamed to the original source file name.

The following options require some clarification:
        - Auto Update
                When this option is selected, data changes are auto-
                matically written to the ROM1 once the user leaves the
                current line.  If this option is NOT selected, the ROM1
                is NOT updated until the user explicitly selects a ROM1
                WRITE.
        - Symaphore Disable/LOW/HIGH
                The symaphore byte can be accessed by the TARGET or the
                HOST without concern for arbitration.  Most people DO NOT
                use it.  As a result, we provided the capability to disable
                it completely.  If the user wants to use this byte,
                he can select HIGH or LOW.  LOW configures ROM1 to decode
                offset 0 (LSB) as the Symaphore byte.  Any access to this
                location will access the Symaphore byte instead of SRAM.
                If HIGH is selected, ROM1 decodes offset 7FFFF (MSB) for
                the Symaphore Byte.  Note that if the user's target socket
                is wired for an EPROM smaller than 4Mbit, they will NOT be
                able to access this offset.

                When 2 or 4 ROM1s are daisy-chained, LOW and HIGH still
                refer to the LSB and MSB bytes. With 2 ROM1s, the MSB
                is at FFFFF.  With 4 ROM1s, the MSB is at 1FFFFF.

                The symaphore byte defaults to "DISABLED" when first
                powered up.  If DALLAS "SMART SOCKETS" are used for
                battery backup, be aware that the Symaphore byte
                configuration will be lost when power is removed from
                ROM1.  It will default back to "DISABLED".


LDROM1.EXE

LDROM1 is the command line loader.  It can be placed in a batch file
to automatically download a file each time it is recompiled.  We provide
complete source code to this loader as a working example of how to use
the ROM1UTIL.OBJ code.  The software is configured with command-line
switchs so that is can be batched.  Type "LDROM1" (without parameters)
to see a complete usage discription.


ROM1UTIL.OBJ, .DOC and .H

ROM1UTIL is a set of routines that allows the user to write custom
applications for ROM1.  We provide the .OBJ file so that they can link
it into their own programs. The ROM1UTIL.H file is an include file
that defines the prototypes for these procedures.  ROM1UTIL.DOC describes
the purpose of each routine.  LDROM1.C was linked with ROM1UTIL.OBJ to
produce LDROM1.EXE.


HARDWARE:

ROM1 is similar to our older TurboROM.  We made the following changes:

        - Added a daisy-chain port for cascading up to 4 ROM1s
        - Changed the download connectors to mini-DINs
        - Added support for up to 4 1-Mbit SRAMs
        - Added hardware to allow one to DISABLE the Symaphore Byte


HARDWARE CONFIGURATION:

ROM1 is configured by one DIP switch and one jumper.  The jumper (J6)
determines where the emulator draws power from.  When a 32-pin cable
is used, J6 should be jumpered pin 1 to 2.  When a 28-pin cable is used
it should be jumpered pin 2 to 3.

The DIP switch configures the emulator for the EPROM size to emulate.  It
simply isolates unused address lines so that it is immune to target wiring
variances on these lines.  When all switches are closed or on, ROM1 is
configured for 4Mbits.  To configure it for 2Mbits, one would open or
switch off the switch labeled "2M".  For 1Mbit EPROMs, one would open
the "2M" switch and the "1M" switch.  This would continue until all
switches would be opened for a 2764 EPROM.

       Ŀ
    O   <-- OFF    O    Please note that the arrow points to the
    F   up  dwn 1  N    open or off postion. This example is
    F   up  dwn 2       configured for 4Mbits. All switches on,
        up  dwn 3       or down on the right.
    S   up  dwn 4  S
    I   up  dwn 5  I
    D   up  dwn 6  D
    E    E
         4Mbits


Note that the DIP switch settings affect ONLY the TARGET'S view of the
SRAM.  The downloaders still have access to ALL available SRAM.

ROM1 uses up to 4, 1Mbit SRAMs.  These are populated sequentially, starting
with U6.  To emulate a 27020 EPROM, one would need to populate locations
U6 and U7.


DAISY-CHAIN CONFIGURATION:

When daisy-chaining ROM1s, it is important to understand how the file
data is split-up between the emulators.  The FIRST BYTE of the file is
placed in the LAST ROM1 in the chain.  This is the one with only ONE
cable connected to it.  The next byte (BYTE 1) is placed in the next
emulator in the chain.  If four ROM1s are in use, the LAST ROM1 in the
chain would hold bytes 0,4,8,C,10....  The NEXT TO THE LAST ROM1 would
hold bytes 1,5,9,D,11....  The ROM1 connected directly to the PC would
hold bytes 3,7,B,F....

When only 2 ROM1s are used, the LAST ROM1 in the chain holds the EVEN
data and the FIRST ROM1 in the chain holds the ODD data.


FEATURE CONNECTOR:

J3 is used for RESET and arbitration options.  It is defined as below:

        1  RESET
        2  /RESET
        3  /WRITE
        4  /WAIT
        5  /BUSRQ
        6  /BUSGNT


Pin 1 is an active high RESET signal.  It is activated during downloads
and tri-stated during emulation.

Pin 2 is an active low RESET signal.  It is activated during downloads
and tri-stated during emulation.

Pin 3 is a /write signal input.  This could be connected to the target
write line if the user wants to write to the EPROM space.  NOTE that the
target must ALLOW writing to this space.  Some targets will NOT generate
a Chip Enable signal to the EPROM during a write cycle.  Others, (the 8031
in particular) has no instructions that allow one to write to this space.

Pin 4 is a /wait output.  It generates wait requests anytime the target
attempts to access the ROM1 WHILE the PC is accessing the SRAM.  This can
be used to affect arbitration if the target honors wait requests.  When
using this signal to insert wait-states, pins 5 and 6 should be jumpered
together.

Pins 5 and 6 are normally shorted together unless bus request/grant
hand-shaking is used.  If these signals are used to affect arbitration, the
bus request signal should be tied to a bus request, DMA request, MASTER or
similar input to the target.  In return, the bus granted signal should be
tied to the appropriate return signal from the target (bus granted, DMA
grant ...).

**** IF ARBITRATION AND DAISY-CHAINING ARE BOTH USED, configure the ROM1s
     as follows:

        - For BUS REQUEST/GRANT arbitration, jumper pins 5 to 6 on all
          ROM1s except 1.  Remove the jumper on the remaining unit and
          connect those pins to the target signals.

        - For READY (or WAIT-STATE) arbitration, jumper pins
          5 and 6 on ALL ROM1s.  Connect pin 4 from ALL ROM1s to the
          WAIT request line on the target.


SUMMARY

This text file is very brief, so if you have any questions, please give us
a call.  A printed manual will be available in several weeks.
